A programmable logic array is a circuit which combines a large number of logical input signals according to the rules of boolean arithmetic to provide an output signal. Usually, a programmable logic array has several input leads and several output leads. Each output signal is the product of Boolean operations upon any of the input signals selected during programming. The input signals are selected by either disconnecting or connecting the input lead which receives the selected input signal to the circuitry which combines the selected input signals to form the output signal. A common method of combining input signals to form an output signal is to first combine one or more input signals in a logical OR function to form "product terms" and then to combine a selected number of the product terms in a logical AND function. In order to be as flexible as possible, the circuitry which combines the input signals must be capable of being connected to any combination of the input leads. In addition, it is desirable that as many of the product terms as possible may be connected to the AND gates which provide the output signals.
An array circuit which performs OR and AND functions as described is shown in FIG. 1. Input leads 10-1 through 10-N receive N input signals 9-1 through 9-N. Fuse array 23 is a means for selectively including or not including input signals 9-1 through 9-N in the M boolean equations which determine product terms 24-1 through 24-M. If the associated fuse 23-X-Y, where 1.ltoreq.X.ltoreq.N and 1.ltoreq.Y.ltoreq.M, for input signal 9-X and product term 24-Y is intact, and the input signal 9-X is a logical 1 (typically 5 volts) then transistor 11-X-Y associated with input signal 9-X and product term 24-Y is on. Thus, the positive voltage source 12 pulls product term 24-Y to a logical 1. Any input signal which is a logical one and is connected to a particular product term pulls that product term to a logical 1; therefore, the transistors associated with that product term and those input signals function as a logical OR gate.
Product term 24-Y is connected to the cathode of associated Schottky diode 14-Y of diode bank 14. When product term 24-Y is a logical 0 (typically 0.5 volts) diode 14-Y is forward biased, and current flows from positive voltage source 12, through resistor 22 and through transistor 15-Y to ground. The current creates a voltage drop across resistor 22; therefore, output terminal 21 is a logical 0. Since any of product terms 24-1 through 24-M can pull the output signal on node 21 to a logical 0, diodes 14-1 through 14-M function as an AND gate which combines product terms 24-1 through 24-M.
Conversely, when product term 24-Y connected to the collector of transistor 15-Y is a logical 1, diode 14-Y is not forward biased and the collector current through transistor 15-Y is drawn from the positive voltage source 12 through one or more of the product term transistors 11-1-Y through 11-N-Y. If all of the product terms 24-1 through 24-M are a logical 1, none of diodes 14-1 through 14-M are forward biased and output terminal 21 is pulled to a logical 1 by positive voltage supply 12 through resistor 22.
Transistors 15-1 through 15-M serve as current sources. Bias circuit 25 provides bias to transistors 15-1 through 15-M. The collector current of NPN transistor 18 is fixed by resistor 20 and transistor 19. The current through resistor 20 is determined by summing voltages from positive voltage source 12 to ground. Thus, EQU V(12)=I.sub.ref R(20)+V.sub.BE (19)+V.sub.BE (18), where (1)
V(12) is the voltage of positive voltage source 12,
I.sub.ref is the current through resistor 20,
R(20) is the resistance of resistor 20,
V.sub.BE (19) is the base to emitter voltage drop of transistor (19), and
V.sub.BE (18) is the base to emitter voltage drop of transistor 18.
The base to emitter voltage drops of transistors 18 and 19 are approximately 0.7 volts. Therefore, EQU I.sub.ref =V(12)-1.4 volts/R(20)
The base current of transistor 19 is negligible compared to I.sub.ref ; thus, the collector current in transistor 18 is approximately equal to I.sub.ref. The base current in transistor 18 is determined by the equation I.sub.B (18)=Ic(18)/.beta.(18), where .beta.(18) is the ratio between the collector current and base current in transistor 18, where I.sub.B (18) is the base current to transistor 18 and I.sub.C (18) is the collector current of transistor 18 (see Streetman, Solid State Electronic Devices, Equation 7-6 (1980), which is hereby incorporated by reference). For each base current value in a transistor there is a corresponding base to emitter voltage drop, as described in Streetman on page 152. Therefore, the base-emitter voltage drop of transistor 18 is that voltage which corresponds to I.sub.B (18)=Ic(18)/.beta.(18). Because the base to emitter junctions of transistors 15-1 through 15-M are connected in parallel with the base to emitter junction of transistor 18, and because transistors 15-1 through 15-M are constructed in the same manner as transistor 18 (i.e., the same physical dimensions, same dopant levels, etc.), the base to emitter voltage of transistors 15-1 through 15-M are equal, and thus the collector currents in transistors 15-1 through 15-M are equal to the collector current in transistor 18. This configuration is called a "current mirror."
When fewer than the M product terms provided in a given programmable logic array are necessary to perform the boolean equation modeled by the array of FIG. 1, all of the fuses in the excess product terms, for example fuses 23-1-X through 23-N-X, must remain intact in order to properly model that boolean equation. For example, in an array where N is equal to 3, and M is equal to 3, and where the boolean equation to be modeled by the array is (AB)+(BC), the equation is modeled using the equivalent equation (ABC)+(AB)+(BC). If input signals, A, B and C are received on input leads 10-1, 10-2 and 10-3, respectively, then fuses 23-3-2 and fuse 23-1-3 are opened. If any of the fuses that are to remain intact are inadvertently opened, this boolean equation cannot be modeled by this circuit and the circuit is useless.
Of importance, transistor 15-1 associated with the product term 24-1 continues to draw current. This current serves no purpose because the equation modeled does not include the product term which uses this current. A product cannot be removed by opening the fuses associated with the product term because opening all the fuses associated with the product term causes a logical 0 output signal regardless of the state of the input signals. If fuses 23-1-1, 23-2-1 and 23-3-1 were opened, the output signal on output terminal 21 would always be logical 0. It is common in a fully programmed array for up to 70% of the product terms to remain unused. Therefore, up to 70% of the power provided to drive the array is wasted.